ST-Ericsson has successfully tested its WIOMING 3D application processor. WIOMING – which stands for WideIO Memory Interface Next Generation – provides a major breakthrough for performance increase and power efficiency in low power mobile devices.
Through silicon via (TSV) and fine pitch bumping technologies enable massive interconnect between DRAM and SOC with very low capacitive and inductive load in interface pins and thus allow significant memory bandwidth increases and to lower the interface power dissipation.
In our testing, the ST-Ericsson WIOMING chip provides 12.8GBytes/s of memory bandwidth which represents a 50% increase over the latest available dual channel LPDDR2 solutions at 533MHz at 20% less power.
And WideIO technology is scalable for future generations of mobile devices to memory bandwidths of > 50GBytes/s by, moving to dual data rate (DDR) mode and combination with existing LPDDRx technology. This will enable unprecedented graphics and CPU performances on smartphones and tablets.
The WIOMING 3D WideIO application processor was developed in cooperation with STMicroelectronics (TSV, silicon process and packaging), CEA-Leti (multi core processor backbone and 3D back side processing) and Cadence (EDA tools and WideIO memory controller). WIOMING was partially funded by the COCOA and 3DIM3 projects in the frame of the European Research project CATRENE.
This test chip has been developed in the context of Platform 2012, a STMicroelectronics/ST-Ericsson corporate initiative involving CEA as a strategic partner. Platform 2012 aims at developing a new generation of many cores arrays in deep submicron. 3D stacking is one of the strategic directions as well as heterogeneous technology integration.