In the last post we explored the performance vs voltage benefits of FD-SOI. In this post we look at the other two key benefits – competitive speed/leakage trade-offs, and optimized power efficiency
Competitive speed/leakage trade-off
Not only does FD-SOI bring extra-speed as explained in the previous post , it also exhibits best-class leakage. As shown in the graph below, representing the same ARM Cortex-A9 critical path as before, the typical leakage at 85°C versus the maximum frequency, for the same leakage budget, FD-SOI at nominal voltage (1.0V) is systematically faster than either the LP process at nominal voltage (1.0V) or the HP process at nominal voltage (0.9V).
Compared Leakage vs. Speed performance of LP, GP, and FD-SOI technologies
The light blue line corresponds actually to the FD-SOI Leakage-Speed curve for Vdd=0.9V. This means that with FD-SOI, we can consider lowering your nominal Vdd (critical to dynamic power consumption) and still produce the same or better performance as LP or HP processes. Then, as shown in the dash blue line extension, forward body biasing (*) on LVT FD-SOI transistor allows the same peak performance as HP to be reached, while higher poly biased transistors achieve the same leakage gain as LP process.
This Leakage vs. Speed benefit is unique to FD-SOI in 28nm. It really combines the best of both LP and HP processes.
* Body-biasing is the capability of applying a variable voltage on the bulk part of the CMOS transistors to either increase its speed (forward-body biasing) at the cost of extra leakage or reduce its leakage (reverse body-biasing) at the cost of a lower performance. Although available in bulk CMOS, body biasing is incomparably more efficient in FD-SOI thanks to the buried oxide isolating the transistor channel from the silicon bulk (back gate action).
Optimized power efficiency
For high-end mobile applications, good performance at the best leakage level is not enough: Reducing total power consumption in the different operating modes which the device uses in typical daily use is key to maximizing battery time.
The chart below shows three different 28nm process flavors and plots the the dynamic power consumption versus the maximum frequency.
Dynamic Power vs. frequency comparisons between LP, HP and FD-SOI
What we can see is that for a given frequency , the total dynamic power consumption is always considerably lower – even if FD-SOI requires a slightly higher supply voltage than 28 “HP” to reach the target frequency. This is due essentially to a lower leakage contribution in the total power of the FD-SOI technology. This behavior can be seen across the whole voltage and corresponding performance range demonstrating clearly that FD-SOI the solution that gives the best power efficiency for mobile devices.
So we have seen that 28nm FD-SOI outperforms existing bulk process technologies on the key parameters for mobile computing devices – more performance at lower power. This is why ST-Ericsson has chosen FD-SOI for its next generation of NovaThor high-performance platforms for smartphones and tablet. Our first product will be sample in the second half of this year.
Per Ingelhag
May 25, 2012 at 10:44 amCan you explain what a WC temperature is (in the figures) … is WC referring to speed or power?
Valery Gravoulet
May 25, 2012 at 1:28 pmThe same applies here for worst case temperature performance as answered in previous post:
Temperature inversion for 28NM bulk and 28NM FDSOI is not occuring for the same voltage. It is around 1.1V – 1.2V for bulk depending of the VT implant, while it is around 700mV- 800mV for FDSOI. It means that above this voltage level, the slowest temperature will be for the highest one (+125C) and below it will be for the lowest one (-40C). Around this threshold voltage , the slowest temperature will be anywhere between -40C and 125C. In the present curves I am really comparing worst case temperature independantly for each processes, so for example the 1.0V points are at 125C for FDSOI and -40C for bulk; while at 0.6V all points are at -40C.
For leakage, this is mentioned as 85degC and this is the same for all processes. So it means that X and Y axis are not doen at the same temperature, however this is to cover the extremes corners for both leakage or dynamic power and performance.
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Alexander
January 10, 2013 at 4:57 pmHello Valery,
I have few questions on the graphs below :
Second graph showing dynamic power vs speed. I understand that dynamic power is actually coming for total power, including leakage. Otherwise it is not reasonable that LP@0.9v will be below HP@0.7v. Right?
Which design you used for simulation of dynamic power? is that just CMOS, FO4 chain, any other benchmark path? Which parasitic Cload was assumed in this simulation to represent dynamic current?
Thanks!
Valery Gravoulet
January 16, 2013 at 2:30 pmHello Alexander,
You are right, the term ‘Dynamic” may be misleading, it includes switching power and leakage power. “Total power” would be more appropriate. The text refers to the point you effectively mention, leakage contribution makes the difference between all processes.
All simulations have been done on a critical path extracted from an Arm Cortex A9 physical implementation in 28NM LP. It ‘s a chain of about 20 logic gates between 2 flip-flops plus associated load cells and a full RC interconnect extraction. The RC contributes about 25% of the total delay. Total power and leakage have been extracted directly from these critical path simulations. The gate activity of this critical path simulation is quite high (> 60%) because only load cells affecting the critical path delay are present and contributes to the leakage on top of switching cells. In a real IP or design you would have a lower activity giving even more weight to the leakage contribution on the total power. So, in that respect, a critical path only simulation is a worst case for FDSOI power benchmarking as high activity will not benefit a process demonstrating a low leakage capability.
Hopes this clarify a bit the simulation methodology.
Note that we have just demonstrated at CES 2013 the excellent power saving capability of FDSOI on a real product. See Live demo of NovaThor L8580, FD-SOI technology at CES 2013 for more details.
Best regards
Alexander
January 20, 2013 at 7:56 amThanks Valery for detailed answer.
Presentation indeed looks impressive with 0.63v operating voltage.
Interesting why articles/presentation talking about ~30-40% power saving, while simple calculation of 0.63v vs 1.1v ratio giving almost 70% power reduction, that is more impressive. Something i missing here that not taken into account?
BTW, S3 used as reference, doing low freq. operations at ~0.9v-0.95v (still using this voltage, achieved 50% power reduction assuming 0.63v for L8580 SoC).
Why all references mention much smaller gain for 28FD?
Valery Gravoulet
January 29, 2013 at 3:54 pmHi Alexander,
Actually articles are only looking at non body biased FDSOI. But one important property of FDSOI is its ability of supporting high body biasing voltage due to the buried oxide. This gives an extra degree of freedom in optimising dynamically the performance of the transistors (Vt adjustement). Achieving 1GHz at 0.63V is most probably obtained with a forward body biasing which is boosting the transistor performance. By reducing the transistor VT, it also increases the transistor leakage so that you will not get the direct 70% reduction, but you will still end-up with the 30 to 50% gain illustrated in most presentations and simulations done with no body biasing. The interest is of course to have a whole SoC operated at 0.63V and only have the CPU power domain in forward body biasing to push its performance to the 1GHz without impacting the overal SOC power consumption. The gain is really architecture dependant but thanks to FDSOI, you really have more trade-off to explore and in any case at least 30 to 40% power gain.