With the recent evolution in smartphone capabilities consumer expectations are rising fast. Ultra-fast multicore Gigahertz processors, stunning 3D graphics, full HD multimedia and high-speed broadband connectivity have become the norm for high-end devices. Consumers expect these features to be delivered in a device that is slim, light and can last for at least as long as their previous phones did. For our customers, the product designers, this translates into requirements for delivering high performance at low power in a cost effective manner. Fully Depleted Silicon On Insulator – or FD-SOI - is a technology that addresses exactly these requirements.
At Mobile World Congress, our CEO Didier Lamouche confirmed during his speech that our next generation NovaThor platform, a successor to the NovaThor L8540, will be using 28nm FD-SOI technology.
FD-SOI is a technology that is available for design today and will allow existing designs in 28nm to benefit today already from significant improvements in performance and power. FD-SOI solves – with less process complexity – scaling, leakage and variability issues to further shrink CMOS technology beyond 28nm.
FD-SOI, like FinFET, is a technology that was initially planned for 20nm nodes and below to overcome traditional bulk CMOS scaling limitations such as high leakage and device variability. However, unlike FinFET, FD-SOI process remains a low-complexity planar process very similar to the traditional CMOS bulk. This allows for a faster process development and ramp-up and an easier design porting for existing designs. The strong collaboration between ST-Ericsson, STMicroelectronics, Leti and Soitec is allows us to already benefit in 28nm from the added value of FD-SOI. The three key benefits realized are leading performance, competitive speed/leakage trade-offs, and optimized power efficiency. This post looks at the performance aspects and a later post will look at the other two benefits.
Leading-edge performance across a wide voltage range
The graph below compares the maximum frequency achievable for a particular critical path of an ARM Cortex™-A9 CPU core implementation, versus the supply voltage Vdd, for a slow corner process (SS) and a worst case temperature.
Each curve represents a specific 28nm process offer.
- 28HP-LVT is a mobile high performance bulk CMOS process. Targeting high CPU performance mobile applications , these processes are derived from fast process flavors with very thin gate oxide and therefore have a limited Vdd overdrive capability (~1.0V) for reliability reasons
- 28LP-LVT is a low power bulk CMOS process. Traditionally used for low power mobile applications, LP processes are based on thicker transistor gate oxide supporting a higher voltage overdrive (up to 1.3V).
- 28FDSOI-LVT is the 28nm FD-SOI process developed by STMicroelectronics. FD-SOI uses a similar gate structure as 28LP, it can also sustain a 1.3V overdrive.
In all process, only low voltage threshold (LVT) transistors are considered. These are the one giving the highest speed performance.
Performance comparison of 28nm technologies
- First observation is that FD-SOI at nominal voltages (0.9V for HP, 1.0V for both LP and FD-SOI) gives similar peak performance to HP processes and more than 35% performance improvement compared to LP at same Vdd.
- Furthermore, higher Vdd tolerance allows for an extra performance boost in FD-SOI that is not possible with HP processes, resulting in better overall peak performance
- At low operating voltages such as Vdd=0.6V, the LP process is either not functional or gives low performance. FD-SOI is equivalent or better than the HP process – but with a much lower leakage and dynamic power consumption as we will see in a later post.
- Thanks to lower process variability than any bulk CMOS process, FD-SOI allows even lower operating voltages (down to 0.5V) at frequencies that are useful for non-CPU intensive processes (200MHz-300MHz) e.g. Hardware accelerated audio or video playback.
So, over a large Vdd range (from 0.5V up to 1.3V), FD-SOI comprehensively outperforms existing bulk CMOS processes dedicated to mobile applications. This extra performance gain can be used either to increase peak performance or to operate at a lower Vdd for the same performance, saving dynamic power.