In the last post we explored the performance vs voltage benefits of FD-SOI. In this post we look at the other two key benefits – competitive speed/leakage trade-offs, and optimized power efficiency

Competitive speed/leakage trade-off

Not only does FD-SOI bring extra-speed as explained in the previous post , it also exhibits best-class leakage. As shown in the graph below, representing the same ARM Cortex-A9 critical path as before, the typical leakage at 85°C versus the maximum frequency, for the same leakage budget, FD-SOI at nominal voltage (1.0V) is systematically faster than either the LP process at nominal voltage (1.0V) or the HP process at nominal voltage (0.9V).

Compared Leakage vs. Speed performance of LP, GP, and FD-SOI technologies

The light blue line corresponds actually to the FD-SOI Leakage-Speed curve for Vdd=0.9V. This means that with FD-SOI, we can consider lowering your nominal Vdd (critical to dynamic power consumption) and still produce the same or better performance as LP or HP processes. Then, as shown in the dash blue line extension, forward body biasing (*) on LVT FD-SOI transistor allows the same peak performance as HP to be reached, while higher poly biased transistors achieve the same leakage gain as LP process.

This Leakage vs. Speed benefit is unique to FD-SOI in 28nm. It really combines the best of both LP and HP processes.

* Body-biasing is the capability of applying a variable voltage on the bulk part of the CMOS transistors to either increase its speed (forward-body biasing) at the cost of extra leakage or reduce its leakage (reverse body-biasing) at the cost of a lower performance. Although available in bulk CMOS, body biasing is incomparably more efficient in FD-SOI thanks to the buried oxide isolating the transistor channel from the silicon bulk (back gate action).

Optimized power efficiency

For high-end mobile applications, good performance at the best leakage level is not enough: Reducing total power consumption in the different operating modes which the device uses in typical daily use is key to maximizing battery time.

The chart below shows three different 28nm process flavors and plots the the dynamic power consumption versus the maximum frequency.

Dynamic Power vs. frequency comparisons between LP, HP and FD-SOI

What we can see is that for a given frequency , the total dynamic power consumption is always considerably lower – even if FD-SOI requires a slightly higher supply voltage than 28 “HP” to reach the target frequency. This is due essentially to a lower leakage contribution in the total power of the FD-SOI technology. This behavior can be seen across the whole voltage and corresponding performance range demonstrating clearly that FD-SOI the solution that gives the best power efficiency for mobile devices.

So we have seen that 28nm FD-SOI outperforms existing bulk process technologies on the key parameters for mobile computing devices – more performance at lower power. This is why ST-Ericsson has chosen FD-SOI for its next generation of NovaThor high-performance platforms for smartphones and tablet. Our first product will be sample in the second half of this year.